What is the appropriate number of channels for a mixed-signal oscilloscope?

1. Introduction to FSMC: FSMC is a flexible static storage controller. The FSMC manages 1GB of space and has 4 banks connected to external memory. Each bank has independent chip select signals and independent timing configuration. The supported memory types are S RAM . PSRAM, NOR/ONENAND, ROM , LCD interface (supports 8080 and 6800 modes), NANDFlash and 16-bit PCCard.

2. In the design, the FPGA is used as the SRAM to drive. The library function is used to implement the FSMC initialization configuration code as follows:

/ / Initialize the external SRAM
Void FSMC_SRAM_Init(void)
{
FSMC_NO RS RAMInitTypeDef FSMC_NORSRAMInitStructure; // definition of structure variables initialized FSMC FSMC_NORSRAM Ti mingInitTypeDef readWri te TIming; // to set the read timing and write timing FSMC pointer variable G PI O_InitTypeDef GPIO_InitStructure; // IO port initialization bus FSMC
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD|RCC_APB2Periph_GPIOE|RCC_APB2Periph_AFIO, ENABLE);
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE); //Enable FSMC clock
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8|GPIO_Pin_9|GPIO_Pin_10|GPIO_Pin_14

|GPIO_Pin_15|GPIO_Pin_0|GPIO_Pin_1
|GPIO_Pin_7|GPIO_Pin_11|GPIO_Pin_12|GPIO_Pin_13|GPIO_Pin_4|GPIO_Pin_5;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; //The IO port is configured as a multiplexed push-pull output GPIO_InitStructure.GPIO_Speed ​​= GPIO_Speed_50MHz;
GPIO_Init(GPIOD, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin=GPIO_Pin_7|GPIO_Pin_8|GPIO_Pin_9

|GPIO_Pin_10|GPIO_Pin_11|GPIO_Pin_12|GPIO_Pin_13|GPIO_Pin_14|GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitStructure.GPIO_Speed ​​= GPIO_Speed_50MHz;
GPIO_Init(GPIOE, &GPIO_InitStructure);


GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_6;
GPIO_InitStructure.GPIO_Speed ​​= GPIO_Speed_50MHz;
GPIO_Init(GPIOE, &GPIO_InitStructure);

readWriteTIming.FSMC_AddressSetupTIme = 14;
readWriteTIming.FSMC_AddressHoldTime = 0x00;
readWriteTiming.FSMC_DataSetupTime = 16;
readWriteTiming.FSMC_BusTurnAroundDuration = 0;
readWriteTiming.FSMC_CLKDivision = 0x00;
readWriteTiming.FSMC_DataLatency = 0x00;
readWriteTiming.FSMC_AccessMode = FSMC_AccessMode_A;



FSMC_NORSRAMInitStructure.FSMC_Bank=FSMC_Bank1_NORSRAM1;
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
FSMC_NORSRAMInitStructure.FSMC_MemoryDataW idt h= FSMC_MemoryDataWidth_16b;
FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode=FSMC_BurstAccessMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_W ai tSignalPolarity = FSMC_WaitSignalPolarity_Low;
FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait=FSMC_AsynchronousWait_Disable;
FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &readWriteTiming;
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &readWriteTiming;
FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM1, ENABLE);
Delay_ms(50);
}

FPGA code:

//fsmc read / write ep4ce6 demo

Module fsmc(
Ab, //address
Db, //data
Wrn, //wr
Rdn, //rd
Resetn, //resetn
Csn, //cs
Clk
);

Input[2:0] ab;
Inout[15:0] db;
Input wrn;
Input rdn;
Input resetn;
Input csn;
Input clk;

reg [15: 0] ina = 16'd0; // for storing data read ARM reg [15: 0] inb = 16'd1;
Reg [15:0] inc = 16'd2;
Reg [15:0] ind = 16'd3;
Reg [15:0] ine = 16'd4;
Reg [15:0] inf = 16'd5;
Reg [15:0] ing = 16'd6;
Reg [15:0] inh = 16'd7;


Reg [15:0] outa;
Reg [15:0] outb;
Reg [15:0] outc;
Reg [15:0] outd;
Reg [15:0] oute;
Reg [15:0] outf;
Reg [15:0] outg;
Reg [15:0] outh;

Wire rd;
Wire wr;

Reg [15:0] indata;

Assign rd = !(csn & rdn); //get rd pulse ____|~~~~|______
Assign wr = !(csn & wrn) ; //get wr pulse ____|~~~~|______

/********* db=indata********* when no read or write operations are performed
********* When writing, db=16'hzzzz**********
********* When doing a read operation db=indata**********/
Assign db = rd? indata:16'hzzzz;


//write data, select eight space writes according to the address line, 16 bits per space always @(negedge wr or negedge resetn)
Begin
If(!resetn)begin
Outa <= 16'h0000;
Outb <= 16'h0000;
Outc <= 16'h0000;
Outd <= 16'h0000;
Oute <= 16'h0000;
Outf <= 16'h0000;
Outg <= 16'h0000;
Outh <= 16'h0000;
End else begin
Case (ab)
3'b000: outa <= db;
3'b001: outb <= db;
3'b010: outc <= db;
3'b011: outd <= db;
3'b100:oute <= db;
3'b101:outf <= db;
3'b110:outg <= db;
3'b111:outh <= db;
Default:;
Endcase
End
End


//red data Select 8 spaces to read according to the address line, 16 bits per space always @(rd or !resetn)
Begin
If(!resetn)indata <= 16'h0000;
Else begin
Case (ab)
3'b000:indata <= ina;
3'b001:indata <= inb;
3'b010:indata <= inc;
3'b011:indata <= ind;
3'b100:indata <= ine;
3'b101:indata <= inf;
3'b110:indata <= ing;
3'b111:indata <= inh;
Default:;
Endcase
End
End
Endmodule