First come to a paragraph in the manual.
Three different clock sources can be used to drive the system clock (SYSCLK)
· HSI oscillator clock
· HSE oscillator clock
· PLL clock
The PLL clock is generally used, followed by evidence.
We can get the clock value through the library function.
Void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
In my system, print the clock value as follows:
SYSCLK: 0x44aa200 //72000000, 72MHz
HCLK: 0x44aa200 //72000000, 72MHz
PCLK1: 0x2255100 //36000000, 36MHz
PCLK2: 0x44aa200 //72000000, 72MHz
ADCCLK: 0x2255100 //36000000, 36MHz
RCC-"CFGR: 0x001D040A // PLL output as system clock
It can be inferred that several prescalers are
AHB prescaler = 1
APB1 prescaler = 2
APB2 prescaler = 1
ADC prescaler = 2
According to the read RCC-"CFGR register value: 0x001D040A, the above speculation is completely correct.
The SWS segment of the CFGR register also states that the PLL output is used as the system clock.
TIM2 uses PCLK1, but note that this section is in the clock tree.
see Attachment
It is known that APB1 prescaler=2, so TIM2CLK = PCLK1*2 = 72MHz.
Therefore, the clock size divided by TIM2 is 72MHz.
My program also proves this
TIM_TimeBaseInitTypeDef tim2_InitStruct;
TIM_DeInit(TIM2);
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);//Enable Timer2 clock.
NVIC_ConfigurationForTimer2();
// PCLK1=36MHz, PSC=36000-1, CK_CNT=36MHz/(PSC+1)=1000
// ARR=2000, 1s/1000 * 2000 = 2s.
tim2_InitStruct.TIM_Prescaler = 36000-1;
tim2_InitStruct.TIM_Period = 2000-1;
tim2_InitStruct.TIM_CounterMode = TIM_CounterMode_Up;
tim2_InitStruct.TIM_ClockDivision = TIM_CKD_DIV1;
tim2_InitStruct.TIM_RepetitionCounter = 0;
TIM_TimeBaseInit(TIM2, &tim2_InitStruct);
TIM_ClearFlag(TIM2, TIM_FLAG_Update);
TIM_ITConfig(TIM2, TIM_IT_Update, ENABLE);//Enables the specified TIM interrupts.
This configuration originally thought that the timing time was 2s, and actually only 1s. Read the manual to understand the reason.
Read more >>>>>>>>>> STM32 learning RCC clock configuration
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