Interpretation of ENC28J60 embedded network interface circuit

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The Ethernet interface implementation scheme with ENC28J60 as the core is designed, and the design method of the hardware architecture of the system is described. Based on a brief introduction to the structure, function and peripheral circuits of the Ethernet controller ENC28J60, the SPI communication between ENC28J60 and Atmega16 is described. This solution not only has low cost, but also achieves a transmission rate of more than 500Kbps, which satisfies the Internet control requirements of embedded systems.

ENC28J60 application in embedded network interface

The ENC28J60 can be used to form network terminal nodes with different functions, such as network servers, Internet-enabled devices, and remote monitoring (data acquisition, diagnostic) devices. Figure 2 shows the hardware circuit schematic of the embedded network interface based on ENC28J60. In the circuit: 2 LED status indicators are mainly used to display the network connection status, including whether the PHY conflicts, whether the connection is established, whether to receive data, connection speed, duplex mode, etc.; Required bias resistor R3 (2kΩ, accuracy is 1%); high-speed LAN electromagnetic isolation module (ie RJ45 Ethernet interface), in application, the physical port of ENC28J60 must be in accordance with IEEE802.3 physical layer specification when connecting with isolation transformer HR901170A, such as RJ45 jack and isolation transformer The spacing should be as small as possible, and the output and input differential signal pairs should be well isolated.

The main controller in the circuit uses Atmel's ATmega16 microcontroller with advanced RISC (Reduced Instruction Set Computer) architecture, 16 kB programmable Flash memory, 512 B EEPROM and 1 kB of on-chip SRAM with rich peripheral interfaces. Its SPI interface allows ATmega16 to communicate with peripherals at high speeds. In this design, the ATmega16 SPI is configured in master mode and the ENC28J60 is slave. The SPI working mode of ATmega16 is set by CPOL and CPHA. According to the SPI read/write timing of ENC28J60, the SPI working mode of ATmega16 should be set to mode 0. ATmega16 synchronizes with the CS pin of ENC28J60. The SPI clock is initiated by the data written to the SPI Transmit Buffer register. The data transmission order on the SPI MOSI (PB5) pin is controlled by the DORD bit of the SPCR register. When set, the LSB (lowest bit) of the data is transmitted first, otherwise the data is The MSB (most significant bit) is sent first. We choose to send the MSB first, and the received data is transferred to the receive buffer register, and the CPU performs right alignment to read the received data from the receive buffer. It should be noted that when multiple data needs to be read from the ENC28J60, even if the ENC28J60 does not require the data of the ATmega16 serial output, write a data to the SPI Transmit buffer to start the SPI interface clock before each data is read. Since the SPI system has only one buffer in the transmit direction and two buffers in the receive direction, it must wait until the shift process is completed before writing to the SPI data register. When receiving data, The current received data needs to be read by accessing the SPI data register before the end of the next byte shifting process, otherwise the first data is lost.