ASIC-class UltraScale architecture elements include massive data streams, highly optimized critical paths, enhanced DSP subsystems, 3D IC interchip bandwidth, massive I/O and memory bandwidth, multi-zone-like ASIC clocking, power management, next-generation security and elimination The wiring is congested. The detailed description of each element is as follows:
--- Massive data stream: Optimized for wide bus, supporting the implementation of several Tb-level throughput and minimum latency;
---Highly optimized critical path: Built-in high-speed memory cascading to eliminate bottlenecks in DSP and packet processing;
--- Enhanced DSP Subsystem: Combines critical path optimization with a new 27x18-bit multiplier and two adders to achieve a huge leap point and IEEE 754 standard floating-point arithmetic performance and efficiency leap;
---3D IC chip bandwidth
Provides inter-chip bandwidth stepping function for 2nd generation 3D IC system integration and new 3D IC large-width memory optimized interface;
--- Massive I/O and memory bandwidth
Significantly reduce latency with multiple hardened ASIC-grade 10/100G Ethernet, Interlaken and PCIe® IP cores to support next-generation memory interface functions;
---Multi-area similar ASIC clock
Multi-area similar to ASIC clocks, delivering low-power clock networks with very low clock skew and high performance scalability;
---Power Management
Provides a wide range of static and dynamic power gating across multiple functional elements for significant energy savings;
---New generation security
Advanced methods for AES bitstream encryption and authentication, key obfuscation and secure device programming;
--- Eliminate wiring congestion
Collaborative optimization with Vivado tools enables over 90% device utilization without sacrificing performance or increasing latency.
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