The interface diagram of Zedboard is as follows:
The modules hanging on the PL side include HDMI, VGA, OLED, etc. The process of driving VGA on the Zedboard will be described in detail below, and the development environment is Vivado 2016.2. Zedboard is a DAC circuit built by a weight resistor network.
For the driving principle of VGA, please see the timing diagram below:
In the program, the line and field sync signals are generated by the counter. Here is a brief introduction to the development process of Vivado. New project under Vivado, select the development board Zedboard, as shown in the figure:
Add the modified project code, here to regenerate the required clock through the clock wizard, the method and quartus are similar, the transplanted project is as follows:
Then run Run Synthesis, Run ImplementaTIon, and Generate Bitstream to generate a .Bit file to download to the FPGA. Here I want to use the function of the online logic analyzer. First, I need to add (* mark_debug="ture" *) to the signal that needs to view the waveform in the code. Even if the signal is not connected in the project, it will not be different. The compiler is optimized. Figure:
We will observe the red, green, and blue signals of the VGA in the logic analyzer. Select Set Up Debug to add the signal of interest.
Note that the clock domain is not mistaken. After setting it, we found that there are more debugging modules in the RTL view.
Then execute Open Target in the Hardware Manager, connect to the target development board, and after the program device is downloaded, the logic analyzer window will automatically come out.
The final display is as follows:
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