The high resolution, low noise, high sensitivity, wide dynamic range, low image distortion, low illumination and real-time performance of video images in security surveillance are the main evaluation technical parameters of IP cameras, so this is affected in the design of IP cameras. Video image acquisition part, video signal processing part and video coding compression part of several main technical parameters become the key of IP camera.
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The video image acquisition part mainly realizes photoelectric conversion of image signals for CMOS or CCD image sensors. The video signal processing part is the ISP part. The main functions include color signal recovery from bayer type to RGB type, RGB to YUV color space conversion, 3A processing (auto white balance, auto exposure, auto focus), image gamma Ma correction, image cropping, color, contrast, brightness control, etc. The video encoding compression part mainly compresses the massive video original video signal into a digital video processing part which is favorable for transmission and storage and can restore the image information with maximum fidelity.
The current IP camera chips for these three key points are mainly concentrated in the following three scenarios.
The first scheme uses a separate chip processing method from the ISP part and the video encoding compression part. The ISP part can use a dedicated ISP chip such as: NXP2400 chip of nextchip, or FPGA (Field Programmable Logic Gate Array) for video image processing. The video encoding compression part may adopt a dedicated integrated chip for hardware compression coding or a digital multimedia processor integrated with a coding compression module.
The second solution uses a single-chip processing method in which the ISP part is integrated with the video encoding compression part, such as HiSilicon's HI3516, HI3517 chip, NXP's ASC886X/ASC885X series chip, TI's TMS320DM814xDaVinci digital media processor chip, etc. The chip also integrates a rich peripheral extension interface to provide sufficient hardware resources support.
The third scheme uses FPGA and other chips to realize video signal processing and encoding functions. This scheme is generally more complicated to design and difficult to develop, and the cost is often high, and the image quality is difficult to guarantee.
Video image acquisition section
The sensors in the video image acquisition section are divided into two types, CCD and CMOS. The working mechanism between the two is different. The CCD image sensor has complicated production process, high cost and large power consumption, but has the advantages of high signal-to-noise ratio, wide dynamic range, high charge conversion efficiency and high output image quality, while the CMOS image sensor has the advantages. The biggest advantage is low power consumption, low cost, simple circuit structure and high integration. With the continuous advancement of technology, the performance of CMOS image sensors is gradually approaching and surpassing CCD.
Therefore, the choice of image sensor in HD IP cameras is still dominated by CMOS.
For HD and Full HD cameras, CMOS's commonly used chips include:
APTINA: MT9P031 (5M@12), MT9P006 (5M@12), AR0331 (3M, WDR), 9M034 (720P, WDR);
OMNIVISION: OV2715 (2M), OV5656 (5M), OV10633 (720P, WDR), OV9715/2 (720P);
PANASONIC: MN34031 (LOWLIGHT, 720P/30WDR, 720P/60), MN34041 (LOWLIGHT, 1080P/30, 1080P/30WDR, 1080P/60);
SONY: IMX035 (LOWLIGHT, 720P/30, 720P/60). IMX036 (LOWLIGHT, 1080P/30, 1080P/60), IMX122 (LOWLIGHT, 1080P/30, 1080P/30WDR, 1080P/60;
ALTANSENS: 3372E.
Between different CMOS chips, the image capture frame rate, wide dynamic range, image output format, minimum illumination, signal-to-noise ratio, chip integration, and image signal output interface are also different, so that IP camera chip matching It produces IP cameras with different pixels such as 2 million pixels, 3 million pixels, 5 million pixels, different wide dynamic range, and different illumination levels.
Video image signal processing section
Due to the difference in image signal output interface of CMOS chip, such as 8/12/16 bitparallelDVP interface, lvdsserialdataHISPI interface. The output data format is also different, such as BAYER-type RGBRAWDATA, or partial image pre-processed YUV data, which requires the back-end image processing ISP chip to support the front-end output interface and output format CMOS chip. If the selected ISP chip does not support the front-end data interface, it also needs to connect the intermediate dedicated interface conversion chip or FPGA logic chip.
In the first scheme, select a dedicated ISP processing chip, such as Nextchip's high-definition multi-function ISPNVP2400, which can support 1.3M/2M pixel video image sensor, directly receive RAW video signal or LVDS signal, after video image processing The chip can output composite analog signals and BT656/BT1120/YC16bits video data streams. Unlike some dedicated ISP chips that only support a single image sensor, it can be seamlessly connected to a variety of image sensors, including Panasonic's MN34031PL, Sony's IMX036LQR/LLR, Aptina's MT9P031, and Omnivision's Ov2715 series of CMOS.
The NVP2400 supports a variety of video image processing functions, including 3A processing, lens malformation correction (LSC) processing, brightness adaptive ACCE ie wide dynamics, 2D/3D digital noise reduction, dead point detection DPC, false color correction, color roll suppression, 64 video image encoding compression part
The encoding compression part of the video image, the current mainstream video encoding compression includes: H.264baseline/main/highprofile encoding, MPEG4SP encoding, MJPEG/JPEGbaseline encoding, etc., HI35LI, HI3517 chip, NXP mentioned in the second scheme The ASC886X/ASC885X family of chips and TI's TMS320DM814xDaVinci digital media processor chips support mainstream video encoding compression standards. Support multi-stream real-time encoding capability HI3516 can support 1080P@30fps+D1@30fps+CIF@30fps+QVGA@30fps+1080pJPEG capture 1fps or 720P@60fps+D1@30fps+CIF@30fps+QVGA@30fps+720pJPEG capture 1fps, HI3517 can support 1080P@60fps+VGA@30fps+1080pJPEG capture 1fps. ASC886X encoding compression capability reaches 1080p/60H.264Highprofile+1080p/40MJPEG, of which ASC8860 supports single image sensor, 1080p/60 real-time video stream encoding, The ASC8861 supports single image sensor, 1080p/60+720p/60 real-time dual stream video encoding, ASC8862 supports dual image sensor, 2x1080p/60 real-time video stream encoding.
Other TI's TMS320DM814xDAVINCI digital media processors support both mainstream video encoding and intelligent video analytics.
The above-mentioned several multimedia processors all integrate the ISP video image processing module. When adopting the first scheme, a dedicated external ISP chip can be used to design a high-definition IP camera chip with these multimedia processors, such as a 2 million IP camera. :(OV2715/MN34041/IMX036/IMX122)+NVP2400+(HI3516/HI3517/ASC886X/ASC885X), you can also directly use the ISP module on these multimedia processors to design the HD IP camera chip of the second scheme, such as 200 10,000-pixel or higher-pixel IP camera: MT9P031/MT9P006/AR0331/MN34041/3372E and other commonly used CMOS chips + HI3516/HI3517/ASC886X/ASC885X/DM814X and other multimedia processors.
Conclusion
Through the general introduction of high-definition IP cameras and the different choices of the three main parts of the IP camera, we can achieve high-definition IP camera design that meets the diversity of different scenarios, and with semiconductor technology, image intelligence analysis technology, video With the rapid development of coding technology, network technology and video surveillance management platform technology, the selection and matching of high-definition IP camera chips will be more diversified and simplified.
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