74hc138 should be familiar to everyone, so do you know how 74hc138 constitutes a 6-64 line decoder? This article introduces you to the 74hc138 to form a 6-64 line decoder method.
74hc13874HC138 decoder accepts 3-bit binary weighted address input (A0, A1 and A2), and when enabled, provides 8 mutually exclusive low-effective outputs (Y0 to Y7). The 74HC138 has 3 unique enable inputs: two active low (E1 and E2) and one active high (E3). Unless E1 and E2 are set low and E3 is set high, the 74HC138 will keep all outputs high. Using this composite enable feature, only 4 74HC138 chips and 1 inverter are needed to easily achieve parallel expansion and combine to become a 1-32 (5-line to 32-line) decoder. Choose one of the low-effective enable input terminals as data input, and use the remaining enable input terminals as the strobe terminal, the 74HC138 can also act as an 8-output demultiplexer, and the unused enable input terminals must remain bound In their respective appropriate high or low effective states.
74hc138 pinout diagram
74hc138 truth table
Use the enable terminal to easily combine two 3/8 decoders into a 4/16 decoder, as shown in the figure below
The analogy is:
Test Results
program
This is the end of the introduction to the 74hc138 forming a 6-64 line decoder. I wonder if you understand it?
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