Talking about the detection method of PLL lock and the intention of simulation detection

1. What are the detection methods for PLL lock, and what are their characteristics?

One is the simplest digital detection. It uses the frequency-divided signal of the input reference and the frequency-divided signal fed back by the VCO to detect the phase in the PFD. The pulse width of the phase-detection is detected by the continuous result clock cycle is less than a certain value. A valid decision rule for locking. This type of detection has a simple decision method, and the result of the judgment is only locked and unlocked.

Talking about the detection method of PLL lock and the intention of simulation detection

Another way is analog lock detection, also known as N-channel drain open-circuit detection. The implementation principle is to directly output the result by XOR operation on the lead and lag pulses of the PFD output. Since the result of XOR is a series of high and low pulses, an external circuit is required for filtering to obtain a level value, and since it is a drain open circuit logic, it is necessary to connect a pull-up resistor to the output. This type of detection is cumbersome to design, and requires careful calculation of the filter capacitor, as well as the pull-up and series capacitors. However, this detection method has many unique features that cannot be replaced by digital detection.

2. Since digital detection is relatively simple, why use analog detection?

Digital detection is better in some very conventional applications. However, when encountering, loss of reference, driving accurate VCXO, high phase discrimination frequency, etc., it often loses its simple advantage, making the detection very unreliable.

Since the digital detection uses the input reference clock, the phase-detection result is processed to obtain the judgment result. Once the reference is lost, the result of the phase-detection cannot be judged, and thus the reference loss is not reported.

When the VCXO is driven more accurately, since the frequency value after the frequency division of the VCXO is very close to the frequency value after the reference frequency division, the error of the phase detection result is too small, and the accuracy of some phase-locked loop decisions is not so high, resulting in even If you don't lock, you still report the loss of lock.

When the frequency of phase discrimination is high, the narrow pulse of phase discrimination cannot be detected correctly by the detection clock, causing false alarm lock. Simulation testing overcomes the above problems.

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